AN ANALYTICAL ACCESS TIME MODEL FOR ON-CHIP CACHE MEMORIES

This paper will describe an analytical access time model for on-chip cache memories which shows the dependence of the cache access time on the cache parameters. This model includes not only general cache parameters such as cache size (C), block size (B), and associativity (A), but also array configuration parameters (Ndwl, Ndbl, Ntwl, and Ntbl) that are responsible for determining the subarray aspect ratio and the number of subarrays. This model makes it possible to quickly evaluate the cache speed using three major cache parameters and the physical RAM array organization parameters without concrete circuit design. A large cache design space can be covered which cannot be done by only SPICE circuit simulation within a limited time. Using the model, the following results are obtained: 1) for given C, B, and A, optimum array configuration parameters can be used to minimize the access time; 2) if the optimum array parameters are used, then the optimum access time is roughly proportional to the log (cache size); and 3) when the optimum array parameters are used, larger block size gives smaller access time but larger associativity does not give smaller access time because of the increase of the data-bus capacitances.