3 LOW DT OPTIONS FOR PLANARIZING THE PRE-METAL DIELECTRIC ON AN ADVANCED DOUBLE POLY BICMOS PROCESS

Three options for planarizing the dielectric separating the polysilicon and first metal in an advanced double poly BiCMOS program are described in terms of both local and long range planarization capabilities. The candidates studied are a sacrificial etchback technique, a high pressure flow of borophosphosilicate glass (BPSG), and a sandwich structure incorporating a spin-on glass (SOG) layer; these are compared to a conventional BPSG flow process. Local planarization was evaluated by profile angles and metal line resistances on a closely spaced step structure, while the ability to planarize large spaces was measured by a characteristic planarization length. All three techniques offer improved planarity with reduced temperature cycles, but the sacrificial etchback process gives the best values of both local and long range planarization. The high pressure flow excels at local planarization, whereas the SOG sandwich structure yields an intermediate planarization length.