MODELS AND EXPERIMENTS ON DEGRADATION OF OXIDIZED SILICON

被引:108
作者
SAH, CT
机构
[1] Solid State Electronics Laboratory, University of Florida, Gainesville, FL 32611
基金
美国国家科学基金会;
关键词
D O I
10.1016/0038-1101(90)90153-6
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
The concepts of electronic and protonic traps are introduced to delineate and classify the fundamental mechanisms of charging, generation, annealing and hydrogenation of electronic or electron and hole traps located in the interfacial (gate-conductor/oxide, oxide/nitride and oxide/silicon), insulator (oxide, nitride and oxynitride) and semiconductor surface layers of silicon MOS transistors and integrated circuits. Two matrix tables, one without tunneling (3 × 3) and one with tunneling (3 × 4) are used to classify the trap charging and electronic injection mechanisms according to the initial and final (band or bound) states of the electronic transition and the energy exchange mechanisms (thermal, optical and Auger-impact). The importance of tunneling to and from traps (TTT) as an oxide charge build-up mechanism is discussed. A theoretical tunneling rate to traps is given showing that traps shallower than about 2 eV from the oxide conduction band edge or 3 eV from the oxide valence band edge cannot be charged by the TTT transitions alone. Experimental examples illustrating the use of these mechanism tables as well as the importance of breaking hydrogen and strained intrinsic bonds by hot electron impact and by thermal hole capture are discussed, including: (i) annealing of the oxide/Si interface traps via hydrogenation during 380C chip bonding and during Fowler-Nordheim tunneling electron injection (FN-TEI) and avalanche electron injection (AEI) stresses, (ii) interface trap generation and positive oxide charge build-up during electron injection via FN-TEI or AEI, and (iii) electrical deactivation of boron and other group-III acceptors (Al, Ga, In) in the silicon surface layer during FNTEI or AEI stresses. Examples at three d.c. bias conditions to delineate the dominant degradation mechanisms in silicon MOS transistors are given showing that trap charging via tunneling (FNTEI, FNTHI and TTT) dominates below about 3.3 V in both n-MOS and p-MOS but trap generation via bond breaking by thermal hole capture may also occur in low voltage p-MOS. Higher than about 10 V, tunneling (FNTEI, FNTHI and TTT) and avalanche injection (AEI and AHI) as well as hydrogen and intrinsic bond-breaking may all be important degradation mechanisms. © 1990.
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收藏
页码:147 / 167
页数:21
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