A 7-MASK CMOS PROCESS WITH SELECTIVE OXIDE DEPOSITION

被引：10

作者：

HORIUCHI, T ^{[1
]}

KANBA, K ^{[1
]}

HOMMA, T ^{[1
]}

MURAO, Y ^{[1
]}

OKUMURA, K ^{[1
]}

机构：

[1] NEC CORP LTD,DIV SYST LSI DEV,SAGAMIHARA,KANAGAWA 229,JAPAN

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 1993年 / 40卷 / 08期

关键词：

D O I：

10.1109/16.223705

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper describes a new 7-mask CMOS process using liquid phase oxide deposition which has selectivity against photoresist. The process modules for self-aligned well and one mask LDD formation are developed. The features of the process are 1) short TAT: 7 masks to first metallization, 2) self-aligned twin retrograde wells with 40% reduction of the p+-n+ spacing compared to conventional wells, and 3) optimal LDD design using different sidewall spacer width for n- and p-channel MOSFET's giving a 10% larger on-current for p-channel MOSFET's compared to a conventional process.

引用

页码：1455 / 1460

页数：6

共 12 条

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