SHORT-CHANNEL-EFFECT-SUPPRESSED SUB-0.1-MU-M GROOVED-GATE MOSFETS WITH W-GATE

被引:39
作者
KIMURA, S
TANAKA, J
NODA, H
TOYABE, T
IHARA, S
机构
[1] HITACHI LTD,CENT RES LAB,PARALLEL COMP APPLICAT PROGRAMS GRP,KOKUBUNJI,TOKYO 185,JAPAN
[2] HITACHI LTD,CENT RES LAB,DEVICE SIMULAT GRP,KOKUBUNJI,TOKYO 185,JAPAN
关键词
D O I
10.1109/16.370030
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Grooved-gate Si MOSFET's with tungsten gates are fabricated using conventional manufacturing technologies, and their short-channel-effect-free characteristics are verified down to a source and drain separation of around 0.1 mu m. Phase shift lithography followed by a side-wall oxide film formation technique achieves a spacing of less than 0.2 mu m between adjacent elevated polysilicons, subsequently resulting in a sub-0.1-mu m source and drain separation in the substrate. Short-channel effects, such as threshold voltage roll-off and punchthrough, are found to be completely suppressed. From device simulations, the potential barrier formed at each grooved-gate corner is considered to he responsible for the suppression of the short-channel effects.
引用
收藏
页码:94 / 100
页数:7
相关论文
共 22 条
[1]   DESIGN OF ION-IMPLANTED MOSFETS WITH VERY SMALL PHYSICAL DIMENSIONS [J].
DENNARD, RH ;
GAENSSLEN, FH ;
YU, HN ;
RIDEOUT, VL ;
BASSOUS, E ;
LEBLANC, AR .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1974, SC 9 (05) :256-268
[2]  
Kimura S., 1991, International Electron Devices Meeting 1991. Technical Digest (Cat. No.91CH3075-9), P950, DOI 10.1109/IEDM.1991.235269
[3]  
Lee K. F., 1993, International Electron Devices Meeting 1993. Technical Digest (Cat. No.93CH3361-3), P131, DOI 10.1109/IEDM.1993.347382
[4]   ANALYSIS OF CONCAVE MOSFET [J].
NATORI, K ;
SASAKI, I ;
MASUOKA, F .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1978, 25 (04) :448-456
[5]   GROOVED GATE MOSFET [J].
NISHIMATSU, S ;
KAWAMOTO, Y ;
MASUDA, H ;
HORI, R ;
MINATO, O .
JAPANESE JOURNAL OF APPLIED PHYSICS, 1977, 16 :179-183
[6]  
Ono M., 1993, International Electron Devices Meeting 1993. Technical Digest (Cat. No.93CH3361-3), P119, DOI 10.1109/IEDM.1993.347385
[7]  
OYAMATSU H, 1993, S VLSI TECHNO, P89
[8]  
ROSNER W, 1988, S VLSI, P9
[9]  
Saito M., 1992, International Electron Devices Meeting 1992. Technical Digest (Cat. No.92CH3211-0), P897, DOI 10.1109/IEDM.1992.307501
[10]  
SAKAO M, 1993, S VLSI TECHNOLOGY, P19