SHORT-CIRCUIT POWER DISSIPATION ESTIMATION FOR CMOS LOGIC GATES

被引：45

作者：

VEMURU, SR

SCHEINBERG, N

机构：

[1] Department of Electrical Engineering, City College of New York

来源：

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-FUNDAMENTAL THEORY AND APPLICATIONS | 1994年 / 41卷 / 11期

关键词：

D O I：

10.1109/81.331533

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Short-circuit power dissipation contributes significantly to the overall power dissipation in ICs. A new formula has been developed for the estimation of short-circuit power dissipation in CMOS logic gates based on the alpha-power law model that includes velocity saturation effects of short channel MOSFETs. A technique is developed for the measurement of short-circuit current and power dissipation of CMOS logic gates for use in circuit simulation. SPICE simulation results show that the new formula is significantly more accurate than existing formulae.

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页码：762 / 765

页数：4

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