SURFACE PLANARITY AND MICROSTRUCTURE OF LOW-TEMPERATURE SILICON SEG AND ELO

被引：10

作者：

ARST, MC ^{[1
]}

RITZ, KN ^{[1
]}

REDKAR, S ^{[1
]}

BORLAND, JO ^{[1
]}

HANN, J ^{[1
]}

CHEN, JT ^{[1
]}

机构：

[1] APPL MAT INC,SANTA CLARA,CA 95051

来源：

JOURNAL OF MATERIALS RESEARCH | 1991年 / 6卷 / 04期

关键词：

D O I：

10.1557/JMR.1991.0784

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

Surface planarity and epi/SiO2 interface characteristics of selective epitaxial growth (SEG) and epitaxial lateral overgrowth (ELO), deposited at 800-950-degrees-C/10 or 25 Torr, have been studied for micron-sized structures. SEG at 860-degrees-C showed superior planarity and reduced ratio of facet width to epi thickness, compared to higher deposition temperatures. Data showed that epi/SiO2 interface defects are greatly reduced for structures parallel to (100) and/or by adding HCl to the source gas, compared to interfaces positioned at standard orientation (110) on a (100) substrate. The transition from SEG to ELO in view of the facet orientations will be discussed. To correlate structural with electrical data, n + /p diodes were fabricated on as-grown and polish planarized SEG. Leakage current values of approximately 100 nA/cm2 could be measured. These are comparable to similar n + /p junctions fabricated on conventional epi.

引用

页码：784 / 791

页数：8

共 11 条

[1]

BORLAND JO, 1988, SOLID STATE TECH JAN, P111

[2] MODEL FOR FACET AND SIDEWALL DEFECT FORMATION DURING SELECTIVE EPITAXIAL-GROWTH OF (001) SILICON [J].