TRILAYER LIFT-OFF METALLIZATION PROCESS USING LOW-TEMPERATURE DEPOSITED SIN(X)

A trilevel resist scheme using low temperature (< 50-degrees-C) deposited SiN(x) rather than Ge for the transfer layer has been developed. This allows use of an optical stepper for lithographic patterning of the emitter-base junctions in GaAs/AlGaAs heterojunction bipolar transistors where a conventional lift-off process using a single level resist often leads to the presence of shorts between metallizations. The plasma-enhanced chemically vapor deposited (PECVD) SiN(x) shows a slightly larger degree of Si-H bonding compared to nitride deposited at higher temperature (275-degrees-C), and is under compressive stress (approximately 5 x 10(10) dyn cm-2) which is considerably relieved upon thermal cycling to 500-degrees-C (approximately 1.5 x 10(10) dyn cm-2 after cooldown). This final stress is approximately a factor of 2 higher than conventional PECVD SiN(x) cycled in the same manner. The adhesion of the low temperature nitride to the underlying polydimethylglutarimide base layer in the trilevel resist is excellent, leading to high yields in the lift-off metallization process. These layers are etched in electron cyclotron resonance discharges of SF6 or O2, respectively, using low additional dc bias (less-than-or-equal-to -100 V) on the sample. Subsequent deposition of the HBT base metallization (Ti/Ag/Au) and lift-off of the trilevel resist produces contacts with excellent edge definition and an absence of shorts between metallization.