RESPONSE OF INTERFACE TRAPS DURING HIGH-TEMPERATURE ANNEALS

We have performed isochronal-annealing measurements on n-channel Si-gate metal-oxide semiconductor field-effect transistors (MOSFETs) to determine the temperature at which interface traps anneal following exposure to 10-keV x-rays. All five of the processes sampled exhibited annealing by 300-degrees-C, although this annealing was generally preceded by an increase in the number of interface traps (N(IT)) at lower temperatures. In particular, N(IT) for two of the processes increased at 100-degrees-C. Additional annealing experiments at 100-degrees-C for a week are consistent with these results. The implications of these results for high-temperature accelerated-annealing rebound testing are discussed.