SUBNANOSECOND 32 BIT MULTIPLIER USING NEGATIVE DIFFERENTIAL RESISTANCE DEVICES

被引：4

作者：

MOHAN, S

MAZUMDER, P

HADDAD, GI

机构：

[1] Department of Electrical Engineering and Computer Science, The University of Michigan, Ann Arbor

来源：

ELECTRONICS LETTERS | 1991年 / 27卷 / 21期

关键词：

DIGITAL INTEGRATED CIRCUITS; INTEGRATED CIRCUITS; NEGATIVE RESISTANCE;

D O I：

10.1049/el:19911198

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Negative differential resistance devices such as resonant tunnelling transistors have been used to design bistable logic circuits. A subnanosecond pipelined multiplier has been designed taking advantage of the fact that the bistable logic circuits simultaneously provide both the logic and the latching functions without any overhead.

引用

页码：1929 / 1931

页数：3

共 9 条

[1] A 500-MHZ 16X16 COMPLEX MULTIPLIER USING SELF-ALIGNED GATE GAAS HETEROSTRUCTURE FET TECHNOLOGY [J].