MICROSTRUCTURE OF HIGH-TEMPERATURE ANNEALED SIMOX WAFER

被引:3
作者
MIYATAKE, H
YAMAGUCHI, Y
MASHIKO, Y
NISHIMURA, T
KOYAMA, H
机构
[1] LSI Research and Development Laboratory, Mitsubishi Electric Corporation, Itami, 664
关键词
D O I
10.1016/0169-4332(89)90136-0
中图分类号
O64 [物理化学(理论化学)、化学物理学];
学科分类号
070304 ; 081704 ;
摘要
High temperature annealing at 1350°C is performed for SIMOX wafers to obtain a high quality thin SOI structure. After the annealing, the buried oxide has sharp interfaces within the two lattice spacings of Si(200), and oxygen precipitates are removed from the top silicon layer. MOSFET's fabricated in the SIMOX wafer with the top silicon layer 70 nm thick exhibit a good stability of threshold voltage with channel lengths down to 0.7 μm. © 1989.
引用
收藏
页码:643 / 646
页数:4
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