CIRCUIT PERFORMANCE OF CMOS TECHNOLOGIES WITH SILICON DIOXIDE AND REOXIDIZED NITRIDED OXIDE GATE DIELECTRICS

The circuit performance of CMOS technologies with silicon dioxide (SiO2) and reoxidized nitrided oxide (RONO) gate dielectrics over the normal regime of digital circuit operation, i.e., VGS ≥5 V and VDS≥ 5 V, has been compared for the first time. The simulation of a simple CMOS inverter has shown that the SiO2 inverter consistently outperforms the RONO inverter over temperatures ranging from 300 to 100 K. This can be attributed mainly to the significantly lower μp (hole mobility) of RONO p-channel devices. At 300 K, μP(RONO) is 14–18% smaller than μ(SiO2) over the entire range of gate biases, while μn(RONO) (electron mobility of n-channel RONO devices) is also smaller than μ(SiO2) and only reaches 96% of μ(at Vgs = 5 V. At 100 K, μn (RONO)/ μ.(SiO2) at Vgs = 5 V is increased to 1.10, however, μp(RONO)/μp(SiO2) at Vgs = 5 V is degraded to 0.59. The dependence of circuit performance on the supply voltage has also been evaluated for the RONO and SiO2 inverters. © 1990 IEEE