1/4-MUM CMOS ISOLATION TECHNIQUE USING SELECTIVE EPITAXY

被引：18

作者：

KASAI, N ^{[1
]}

ENDO, N ^{[1
]}

ISHITANI, A ^{[1
]}

KITAJIMA, H ^{[1
]}

机构：

[1] NEC CORP,FUNDAMENTAL RES LABS,KAWASAKI,KANAGAWA 213,JAPAN

来源：

关键词：

D O I：

10.1109/T-ED.1987.23088

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

引用

页码：1331 / 1336

页数：6

共 15 条

[1] BORLAND JO, 1985, SOLID STATE TECHNOL, V28, P141
[2] ENDO N, 1986, IEEE T ELECTRON DEV, V33, P1659, DOI 10.1109/T-ED.1986.22725
[3] ENDO N, 1983, DEC IEDM, P31
[4] ENDO N, 1985, 43RD P ANN DEV RES C
[5] ESTREICH DB, 1978, DEC IEDM, P230
[6] IIZUKA T, 1981, DEC IEDM, P380
[7] FACET FORMATION IN SELECTIVE SILICON EPITAXIAL-GROWTH
ISHITANI, A
KITAJIMA, H
ENDO, N
KASAI, N
[J]. JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS, 1985, 24 (10): : 1267 - 1269
[8] CMOS DEVICE ISOLATION USING THE SELECTIVE-ETCH-AND-REFILL-WITH-EPI (SEREPI) PROCESS
KAMINS, TI
CHIANG, SY
[J]. IEEE ELECTRON DEVICE LETTERS, 1985, 6 (12) : 617 - 619
[9] KASAI N, 1985, DEC IEDM 85, P419
[10] KUROSAWA K, 1981, DEC IEDM, P384