ANALYSIS AND MODELING OF PARASITIC SUBSTRATE COUPLING IN CMOS CIRCUITS

被引：18

作者：

ARAGONES, X ^{[1
]}

MOLL, F ^{[1
]}

ROCA, M ^{[1
]}

RUBIO, A ^{[1
]}

机构：

[1] UNIV ILLES BALEARS,FAC SCI,DEPT PHYS,E-07071 PALMA DE MALLORCA,SPAIN

来源：

IEE PROCEEDINGS-CIRCUITS DEVICES AND SYSTEMS | 1995年 / 142卷 / 05期

关键词：

CMOS TECHNOLOGY; PARASITIC CAPACITANCES; SUBSTRATE NOISE ANALYSIS; MIXED-SIGNAL CIRCUITS; RAM ERRORS; VLSI;

D O I：

10.1049/ip-cds:19952164

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Analysis of the substrate coupling in integrated circuits is done taking into account technology and layout parameters for different types and location of transistors using a device-level simulator. The noise coupling tendencies of IC scaling are analysed, following interest in advanced technologies. The potential for permanent errors is shown in the case of a RAM cell. A circuit-level model for the coupling mechanism is proposed. The implementation of an IC for experimentation, and the measurements obtained, are discussed.

引用

页码：307 / 312

页数：6

共 12 条

[1] MODELING AND SIMULATION OF INTERCONNECTION DELAYS AND CROSSTALKS IN HIGH-SPEED INTEGRATED-CIRCUITS [J].

GAO, DS ;

YANG, AT ;

KANG, SM .

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, 1990, 37 (01) :1-9

[2] A SIMPLE APPROACH TO MODELING CROSS-TALK IN INTEGRATED-CIRCUITS [J].

JOARDAR, K .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1994, 29 (10) :1212-1219

[3]

MERRILL RB, 1994, DEC P INT EL DEV M S, P433

[4]

NING ZQ, 1987, IEEE T ELECTRON DEV, V34, P644, DOI 10.1109/T-ED.1987.22975

[5] AN APPROACH TO THE ANALYSIS AND DETECTION OF CROSSTALK FAULTS IN DIGITAL VLSI CIRCUITS [J].

RUBIO, A ;

ITAZAKI, N ;

XU, XO ;

KINOSHITA, K .

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1994, 13 (03) :387-395

[6] CLOSED-FORM EXPRESSIONS FOR INTERCONNECTION DELAY, COUPLING, AND CROSSTALK IN VLSIS [J].

SAKURAI, T .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 1993, 40 (01) :118-124

[7]

SHOJI M, 1988, CMOS DIGITAL CIRCUIT

[8] ANALYSIS OF CROSSTALK INTERFERENCE IN CMOS INTEGRATED-CIRCUITS [J].

SICARD, E ;

RUBIO, A .

IEEE TRANSACTIONS ON ELECTROMAGNETIC COMPATIBILITY, 1992, 34 (02) :124-129

[9] ADDRESSING SUBSTRATE COUPLING IN MIXED-MODE ICS - SIMULATION AND POWER DISTRIBUTION SYNTHESIS [J].

STANISIC, BR ;

VERGHESE, NK ;

RUTENBAR, RA ;

CARLEY, LR ;

ALLSTOT, DJ .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1994, 29 (03) :226-238

[10] EXPERIMENTAL RESULTS AND MODELING TECHNIQUES FOR SUBSTRATE NOISE IN MIXED-SIGNAL INTEGRATED-CIRCUITS [J].

SU, DK ;

LOINAZ, MJ ;

MASUI, S ;

WOOLEY, BA .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1993, 28 (04) :420-430

← 1 2 →