A 4-MBIT DRAM WITH FOLDED-BIT-LINE ADAPTIVE SIDEWALL-ISOLATED CAPACITOR (FASIC) CELL

被引:6
作者
MASHIKO, K
NAGATOMO, M
ARIMOTO, K
MATSUDA, Y
FURUTANI, K
MATSUKAWA, T
YAMADA, M
YOSHIHARA, T
NAKANO, T
机构
[1] Mitsubishi Electric Corp, Jpn, Mitsubishi Electric Corp, Jpn
关键词
D O I
10.1109/JSSC.1987.1052794
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
DATA STORAGE, DIGITAL
引用
收藏
页码:643 / 650
页数:8
相关论文
共 21 条
[1]  
ELAHY M, 1984, DEC IEDM, P248
[2]   AN EXPERIMENTAL 4-MBIT CMOS DRAM [J].
FURUYAMA, T ;
OHSAWA, T ;
WATANABE, Y ;
ISHIUCHI, H ;
WATANABE, T ;
TANAKA, T ;
NATORI, K ;
OZAWA, O .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1986, 21 (05) :605-611
[3]   HIGH SENSITIVITY CHARGE-TRANSFER SENSE AMPLIFIER [J].
HELLER, LG ;
SPAMPINATO, DP ;
YAO, YL .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1976, 11 (05) :596-601
[4]   A SUBSTRATE-PLATE TRENCH-CAPACITOR (SPT) MEMORY CELL FOR DYNAMIC RAMS [J].
LU, NCC ;
COTTRELL, PE ;
CRAIG, WJ ;
DASH, S ;
CRITCHLOW, DL ;
MOHLER, RL ;
MACHESNEY, BJ ;
NING, TH ;
NOBLE, WP ;
PARENT, RM ;
SCHEUERLEIN, RE ;
SPROGIS, EJ ;
TERMAN, LM .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1986, 21 (05) :627-634
[5]  
MASHIKO K, 1987, FEB ISSCC, P12
[6]  
MASHIKO K, 1984, FEB ISSCC, P98
[7]   THE DESIGN AND PERFORMANCE OF CMOS 256K BIT DRAM DEVICES [J].
MOHSEN, A ;
KUNG, RI ;
SIMONSEN, CJ ;
SCHUTZ, J ;
MADLAND, PD ;
HAMDY, EZ ;
BOHR, MT .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1984, 19 (05) :610-618
[8]  
NAGATOMO M, 1986, DEC IEDM LOS ANG, P144
[9]  
NAKAJIMA S, 1984, DEC IEDM, P240
[10]  
NAKAMURA K, 1984, DEC IEDM, P236