A 4-MB CMOS SRAM WITH A PMOS THIN-FILM-TRANSISTOR LOAD CELL

A 4-Mb (512K words by 8 b) CMOS static RAM (SRAM) with a PMOS thin-film-transistor (TFT) load cell has been developed [12]. Utilizing the PMOS TFT as a memory cell load, the RAM can obtain a much larger data retention margin than a conventional high-resistive load type cell. An internal voltage down converter (VDC) architecture with an external supply voltage level sensor not only realizes a highly reliable 0.5- μm MOS transistor operation but also a sufficiently low standby power dissipation characteristic for data battery-backup application. A self-aligned equalized level sensing scheme can minimize the sensing delay for a local sense amplifier to drive a large load capacitance of a global sensing bus line. The RAM is fabricated using a half-micrometer, triple-poly, and double-aluminum with dual gate oxide thickness CMOS process technology. The RAM operates under a single 5-V supply voltage with 23-ns typical address access time and 20- and 70-mA operation current at 10 and 40 MHz, respectively. © 1990 IEEE