COUPLING BETWEEN THE FRONT AND BACK INTERFACES IN THE GATE-CONTROLLED P+PN+ DIODE ON SILICON-ON-INSULATOR

被引：1

作者：

MORAGUES, JM ^{[1
]}

BOUZIDI, J ^{[1
]}

CIANTAR, E ^{[1
]}

JERISIAN, R ^{[1
]}

OUALID, J ^{[1
]}

CRISTOLOVEANU, S ^{[1
]}

机构：

[1] INST NATL POLYTECH GRENOBLE,ENSERG,LPCS,F-38016 GRENOBLE,FRANCE

来源：

MICROELECTRONICS JOURNAL | 1994年 / 25卷 / 04期

关键词：

D O I：

10.1016/0026-2692(94)90181-3

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Coupling between the front and back interfaces of gate-controlled diodes fabricated on thin-film silicon-on-insulator (SOI) structures is investigated. Lim and Fossum's model has been modified to take into account the influence of the reverse bias, V-R, applied to the diode junction. This model is verified by capacitance, leakage current and charge pumping measurements performed by varying the front and back gate voltage as well as V-R. The study demonstrates that the intensity of the interface coupling depends on the thicknesses of the gate and buried oxides, SOI layer thickness, and dopings N-1 and N-2 near the two interfaces. Appropriate methods are used to extract these parameters.

引用

页码：307 / 322

页数：16

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