OPTIMIZATION OF GATE OXIDE N2O ANNEAL FOR CMOSFETS AT ROOM AND CRYOGENIC TEMPERATURES

ThiS paper presents a study of the impact of gate-oxide N2O anneal on CMOSFET's characteristics, device reliability and inverter speed at 300 K and 85 K. Two oxide thicknesses (60 and 110 angstrom) and five N2O anneal conditions (900 approximately 950-degrees-C, 5 approximately 40 min) plus nonnitrided process and channel lengths from 0.2 to 2 mum were studied to establish the correlation between the nitrogen concentration at Si/SiO2 interface and the relative merits of the resultant devices. We concluded that one simple postoxidation N2O anneal step can increase CMOSFET's lifetime by 4 approximately 10 times, effectively suppress boron penetration from the P+ poly-Si gate of P-MOSFET's without sacrificing CMOS inverter speed. We also found that the benefits in terms of the improved interface hardness and charge trapping characteristic still exist at cryogenic temperature. All these improvements are found to be closely correlated to the nitrogen concentration incorporated at the Si/SiO2 interface. The optimal N2O anneal occurs somewhere at around 2% of nitrogen incorporation at Si/SiO2 interface which can be realized by annealing 60 approximately 110 angstrom oxides at 950-degrees-C for 5 min or 900-degrees-C for 20 min.