Technology and reliability constrained future copper interconnects - Part II: Performance implications

被引：100

作者：

Kapur, P ^{[1
]}

Chandra, G ^{[1
]}

McVittie, JP ^{[1
]}

Saraswat, KC ^{[1
]}

机构：

[1] Stanford Univ, Dept Elect Engn, Stanford, CA 94305 USA

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 2002年 / 49卷 / 04期

关键词：

cross talk; delay; interconnect performance; repeater power; repeaters; wire inductance;

D O I：

10.1109/16.992868

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This work extends the realistic resistance modeling of on-chip copper interconnects to assess its impact on key interconnect performance metrics. As quantified in Part I of this work, the effective resistivity of copper is not only significantly larger than its ideal, bulk value but also highly dependent on technology and reliability constraints. Performance is quantified under various technological conditions in the future. In particular, wire delay is extensively addressed. Further, the impact of optimal repeater insertion to improve these parameters is also studied using realistic resistance trends. The impact of technologically constrained resistance on power penalty arising from repeater insertion is briefly addressed. Where relevant, aforementioned results are contrasted with those obtained using ideal copper resistivity.

引用

页码：598 / 604

页数：7

共 20 条

[1]

[Anonymous], 1999, INT TECHNOLOGY ROADM

[2]

Bakoglu H., 1990, CIRCUITS INTERCONNEC

[3]

Banerjee K, 2001, DES AUT CON, P798, DOI 10.1109/DAC.2001.935615

[4]

Banerjee K., 2000, Proc. IRPS, P354

[5] Influence of line dimensions on the resistance of Cu interconnections [J].

Chen, F ;

Gardner, D .

IEEE ELECTRON DEVICE LETTERS, 1998, 19 (12) :508-510

[6]

Dally W, 2008, DIGITAL SYSTEMS ENG

[7]

Davis J. A., 1999, 1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325), P165, DOI 10.1109/VLSIT.1999.799395

[8]

Davis J. A., 1999, Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247), P227, DOI 10.1109/IITC.1999.787129

[9] A stochastic wire-length distribution for gigascale integration (GSI) - Part I: Derivation and validation [J].

Davis, JA ;

De, VK ;

Meindl, JD .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 1998, 45 (03) :580-589

[10] Compact distributed RLC interconnect models - Part I: Single line transient, time delay, and overshoot expressions [J].

Davis, JA ;

Meindl, JD .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 2000, 47 (11) :2068-2077

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