The role of native traps on the tunneling characteristics of ultra-thin (1.5-3 nm) oxides

In this paper we report experiments and simulations on thin oxide (1.5-3 nm) MOS devices, showing that native traps can play a dominant role in the tunneling characteristics of such oxides. The number of traps, and thus their role on the tunneling current, can be minimized by careful and simple processing: in this case traps affect the tunneling current in relatively thick oxides while their role vanishes at oxide thicknesses of 2 nm and below.