Impact of CMOS process scaling and SOI on the soft error rates of logic processes

被引：78

作者：

Hareland, S ^{[1
]}

Maiz, J ^{[1
]}

Alavi, M ^{[1
]}

Mistry, K ^{[1
]}

Walsta, S ^{[1
]}

Dai, CH ^{[1
]}

机构：

[1] Intel Corp, Logic Technol Dev, Hillsboro, OR USA

来源：

2001 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS | 2001年

关键词：

D O I：

10.1109/VLSIT.2001.934953

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

Technology scaling, a reduction in operating voltages, and the increase in cache size and circuit complexity have been key enablers to achieving the performance improvement expectation dictated by Moore's Law. The resulting reduction in the node charge of circuit latches and cache cells has resulted in an ever increasing soft error rate (SER) estimation for logic components. This paper will report the SER impact of process scaling over four technology generations (0.35, 0.25, 0.18, 0.13 mum) and provide an experimental assessment of alpha and, for the first time, neutron SER on advanced SOI processes, which have been considered as a possible method to reduce the SER of advanced technologies.

引用

页码：73 / 74

页数：2

共 8 条

[1] A high performance 0.25 mu m logic technology optimized for 1.8V operation [J].

Bohr, M ;

Ahmed, SS ;

Ahmed, SU ;

Bost, M ;

Ghani, T ;

Greason, J ;

Hainsey, R ;

Jan, C ;

Packan, P ;

Sivakumar, S ;

Thompson, S ;

Tsai, J ;

Yang, S .

IEDM - INTERNATIONAL ELECTRON DEVICES MEETING, TECHNICAL DIGEST 1996, 1996, :847-850

[2]

BOHR M, 1994, INTERNATIONAL ELECTRON DEVICES MEETING 1994 - IEDM TECHNICAL DIGEST, P273, DOI 10.1109/IEDM.1994.383414

[3] Scalability of partially depleted SOI technology for sub-0.25μm logic applications [J].

Chau, R ;

Arghavani, R ;

Alavi, M ;

Douglas, D ;

Greason, J ;

Green, R ;

Tyagi, S ;

Xu, J ;

Packan, P ;

Yu, S ;

Liang, CL .

INTERNATIONAL ELECTRON DEVICES MEETING - 1997, TECHNICAL DIGEST, 1997, :591-594

[4] THE LOS-ALAMOS-NATIONAL-LABORATORY SPALLATION NEUTRON SOURCES [J].

LISOWSKI, PW ;

BOWMAN, CD ;

RUSSELL, GJ ;

WENDER, SA .

NUCLEAR SCIENCE AND ENGINEERING, 1990, 106 (02) :208-218

[5] Parasitic bipolar gain reduction and the optimization of 0.25-μm partially depleted SOI MOSFET's [J].

Mistry, KR ;

Sleight, JW ;

Grula, G ;

Flatley, R ;

Miner, B ;

Bair, LA ;

Antoniadis, DA .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 1999, 46 (11) :2201-2209

[6]

TOSAKA Y, 2000, 4 ANN SRC INT SEMATE

[7] A 130 nm generation logic technology featuring 70nm transistors, dual Vt transistors and 6 layers of Cu interconnects [J].

Tyagi, S ;

Alavi, M ;

Bigwood, R ;

Bramblett, T ;

Brandenburg, J ;

Chen, W ;

Crew, B ;

Hussein, M ;

Jacob, P ;

Kenyon, C ;

Lo, C ;

Mcintyre, B ;

Ma, Z ;

Moon, P ;

Nguyen, P ;

Rumaner, L ;

Schweinfurth, R ;

Sivakumar, S ;

Stettler, M ;

Thompson, S ;

Tufts, B ;

Xu, J ;

Yang, S ;

Bohr, M .

INTERNATIONAL ELECTRON DEVICES MEETING 2000, TECHNICAL DIGEST, 2000, :567-570

[8] A high performance 180 nm generation logic technology [J].

Yang, S ;

Ahmed, S ;

Arcot, B ;

Arghavani, R ;

Bai, P ;

Chambers, S ;

Charvat, P ;

Cotner, R ;

Gasser, R ;

Ghani, T ;

Hussein, M ;

Jan, C ;

Kardas, C ;

Maiz, J ;

McGregor, F ;

McIntyre, B ;

Nguyen, P ;

Packan, P ;

Post, I ;

Sivakumar, S ;

Steigerwald, J ;

Taylor, M ;

Tufts, B ;

Tyagi, S ;

Bohr, M .

INTERNATIONAL ELECTRON DEVICES MEETING 1998 - TECHNICAL DIGEST, 1998, :197-200

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