Hot carrier effects in nMOSFETs in 0.1μm CMOS technology

被引：59

作者：

Li, E ^{[1
]}

Rosenbaum, E ^{[1
]}

Tao, J ^{[1
]}

Yeap, GCF ^{[1
]}

Lin, MR ^{[1
]}

Fang, P ^{[1
]}

机构：

[1] Univ Illinois, Dept Elect & Comp Engn, Urbana, IL 61801 USA

来源：

1999 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM PROCEEDINGS - 37TH ANNUAL | 1999年

关键词：

D O I：

10.1109/RELPHY.1999.761622

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Recent studies show that, for a given technology, as the effective channel length is scaled down towards 0.1 mu m, the worst case hot carrier stress condition for nMOSFETs switches from I-b,I-peak (peak substrate current bias condition) to V-g = V-d. In this paper, we demonstrate that the worst case stress condition is determined by the ratio of I-b\(Ib,peak) to I-b\(Vg=Vd). Post-metallization anneal in deuterium similarly improves hot carrier lifetime under bias at I-b,I-peak and V-g = V-d.

引用

页码：253 / 258

页数：6

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