Diagnosis of multifaults in analogue circuits using multilayer perceptrons

被引:30
作者
Maidon, Y [1 ]
Jervis, BW [1 ]
Dutton, N [1 ]
Lesage, S [1 ]
机构
[1] SHEFFIELD HALLAM UNIV,SCH ENGN,SHEFFIELD S1 1WB,S YORKSHIRE,ENGLAND
来源
IEE PROCEEDINGS-CIRCUITS DEVICES AND SYSTEMS | 1997年 / 144卷 / 03期
关键词
analogue circuits; multilayer perceptrons; multiple fault diagnosis;
D O I
10.1049/ip-cds:19971146
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
It is shown, by means of an example, how multiple faults in bipolar analogue integrated circuits can be diagnosed, and their resistances determined, from the magnitudes of the Fourier harmonics in the spectrum of the circuit responses to a sinusoidal input test signal using a two-stage multilayer perceptron (MLP) artificial neural network arrangement to classify the responses to the corresponding fault. A sensitivity analysis is performed to identify those harmonic amplitudes which are most sensitive to the faults, and also to which faults the functioning of the circuit under test is most sensitive. The experimental and simulation procedures are described. The procedures adopted for data preprocessing and for training the MLPs are given. One hundred percent diagnostic accuracy was achieved, and most resistances were determined with tolerable accuracy.
引用
收藏
页码:149 / 154
页数:6
相关论文
共 18 条
[1]   FAULT-DIAGNOSIS OF ANALOG CIRCUITS [J].
BANDLER, JW ;
SALAMA, AE .
PROCEEDINGS OF THE IEEE, 1985, 73 (08) :1279-1325
[2]   SUPPLY CURRENT TESTING OF MIXED ANALOG AND DIGITAL ICS [J].
BELL, IM ;
CAMPLIN, DA ;
TAYLOR, GE ;
BANNISTER, BR .
ELECTRONICS LETTERS, 1991, 27 (17) :1581-1583
[3]   APPLICATION OF KOHONEN AND SUPERVISED FORCED ORGANIZATION MAPS TO FAULT-DIAGNOSIS IN CMOS OPAMPS [J].
COLLINS, P ;
YU, S ;
ECKERSALL, KR ;
JERVIS, BW ;
BELL, IM ;
TAYLOR, GE .
ELECTRONICS LETTERS, 1994, 30 (22) :1846-1847
[4]   TIME-DOMAIN TESTING STRATEGIES AND FAULT-DIAGNOSIS FOR ANALOG SYSTEMS [J].
DAI, H ;
SOUDERS, TM .
IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, 1990, 39 (01) :157-162
[5]   A COMPLETE SCHEME OF BUILT-IN SELF-TEST (BIST) STRUCTURE FOR FAULT-DIAGNOSIS IN ANALOG CIRCUITS AND SYSTEMS [J].
HATZOPOULOS, AA ;
SISKOS, S ;
KONTOLEON, JM .
IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, 1993, 42 (03) :689-694
[6]  
LIPPMANN RP, 1987, IEEE ASSP MAGAZI APR, P4
[7]  
MAIDON Y, 1995, 6 EUR S REL EL DEV F
[8]  
MAIDON Y, 1995, MIX SIGN TEST WORKSH
[9]  
MEADOR J, INT JOINT C NEUR NET, V1, P269
[10]   SUPPLY CURRENT TESTING IN LINEAR BIPOLAR ICS [J].
PAPAKOSTAS, DK ;
HATZOPOULOS, AA .
ELECTRONICS LETTERS, 1994, 30 (02) :128-130