A Bipolar-Selected Phase Change Memory Featuring Multi-Level Cell Storage

被引：185

作者：

Bedeschi, Ferdinando ^{[1
]}

Fackenthal, Rich ^{[2
]}

Resta, Claudio ^{[3
]}

Donze, Enzo Michele ^{[1
]}

Jagasivamani, Meenatchi ^{[2
]}

Buda, Egidio Cassiodoro ^{[1
]}

Pellizzer, Fabio ^{[1
]}

Chow, David W. ^{[2
]}

Cabrini, Alessandro ^{[4
]}

Calvi, Giacomo Matteo Angelo ^{[4
]}

Faravelli, Roberto ^{[4
]}

Fantini, Andrea ^{[4
]}

Torelli, Guido ^{[4
]}

Mills, Duane ^{[2
]}

Gastaldi, Roberto ^{[1
]}

Casagrande, Giulio ^{[1
]}

机构：

[1] Numonyx, I-20041 Agrate Brianza, Italy

[2] Numonyx, Folsom, CA 95630 USA

[3] Studio Microelect & STMicroelect, Pavia, Italy

[4] Univ Pavia, Dept Elect, I-27100 Pavia, Italy

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2009年 / 44卷 / 01期

关键词：

D O I：

10.1109/JSSC.2008.2006439

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, a 90-nm 128-M cell non-volatile memory based on phase-change Ge-2-Sb-2-Te-5, alloy is presented. Memory cells are bipolar selected, and art based on a mu trench architecture. Experimental investigation on multi-level cell (MLC) storage is addressed exploiting the chip MLC capability. To this end, a programming algorithm suitable for 2 bit/cell storage achieving tightly placed inner states (in terms of cell current or resistance) is proposed. Measurements showed the possibility of placing the required distinct cell current distributions, thus demonstrating the feasibility of the MLC phase-change memory (PCM) storage concept. Endurance tests were also carried out. Cumulative distributions after 2-bit/cell programming before cycling and after 100 k program cycles followed by 1h/150 degrees C bake are presented. Experimental results on MLC endurance are also provided from a 180-nm 8-Mb PCM demonstrator with the same mu trench cell structure.

引用

页码：217 / 227

页数：11

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