Deep-submicronCMOS process integration of HfO2 gate dielectric with poly-Si gate

被引:6
作者
Lu, Q [1 ]
Lin, R [1 ]
Takeuchi, H [1 ]
King, TJ [1 ]
Hu, CM [1 ]
Onishi, K [1 ]
Choi, R [1 ]
Kang, CS [1 ]
Lee, JC [1 ]
机构
[1] Univ Calif Berkeley, Dept Elect Engn & Comp Sci, Berkeley, CA 94720 USA
来源
2001 INTERNATIONAL SEMICONDUCTOR DEVICE RESEARCH SYMPOSIUM, PROCEEDINGS | 2001年
关键词
D O I
10.1109/ISDRS.2001.984521
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
We demonstrate the integration of sputter-deposited ultra-thin HfO2 gate dielectric into a sub-100 nm gate length CMOS process using poly-Si as the gate material. Good device characteristics have been observed down to 70 nm physical gate length, and an equivalent gate oxide thickness (EOT) of 11 Angstrom has been achieved. Both p-FETs and n-FETs with HfO2 gate dielectric show similar to10(4)x lower gate leakage than SiO2 with comparable EOT. Data an, model suggest that the gate leakage of HfO2 will be 100x lower than that of SiO2 down to 5 Angstrom EOT.
引用
收藏
页码:377 / 380
页数:4
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