Highly reliable polysilicon oxide grown by electron cyclotron resonance nitrous oxide plasma

被引：24

作者：

Lee, NI ^{[1
]}

Lee, JW ^{[1
]}

Hur, SH ^{[1
]}

Kim, HS ^{[1
]}

Han, CH ^{[1
]}

机构：

[1] KOREA ADV INST SCI & TECHNOL,DEPT ELECT ENGN,YUSONG GU,TAEJON 305701,SOUTH KOREA

来源：

IEEE ELECTRON DEVICE LETTERS | 1997年 / 18卷 / 10期

关键词：

D O I：

10.1109/55.624924

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Highly reliable inter-polysilicon oxide (polyoxide) for nonvolatile memory applications has been achieved using electron cyclotron resonance (ECR) N2O-plasma, It is demonstrated that the N2O-plasma polyoxide grown on doped poly-Si has a low leakage current and high breakdown field due to a smooth polyoxide/poly-Si interface and nitrogen incorporation during oxidation, Moreover, the polyoxide has much less electron trapping and over one order larger charge-to-breakdown (Q(bd)) up to 10 C/cm(2) than thermal polyoxide. The N2O-plasma polyoxide can be a good choice for interpoly dielectric of nonvolatile memories.

引用

页码：486 / 488

页数：3

共 9 条

[1] Optimizing polysilicon thin-film transistor performance with chemical-mechanical polishing and hydrogenation [J].

Chan, ABY ;

Nguyen, CT ;

Ko, PK ;

Wong, M ;

Kumar, A ;

Sin, J ;

Wong, SS .

IEEE ELECTRON DEVICE LETTERS, 1996, 17 (11) :518-520

[2]

HEDGE RI, 1995, APPL PHYS LETT, V66, P2882

[3]

HENDRICKS M, 1980, J ELECTROCHEM SOC, V127, P705

[4] POLYCRYSTALLINE SILICON OXIDATION METHOD IMPROVING SURFACE-ROUGHNESS AT THE OXIDE POLYCRYSTALLINE SILICON INTERFACE [J].

JUN, MC ;

KIM, YS ;

HAN, MK ;

KIM, JW ;

KIM, KB .

APPLIED PHYSICS LETTERS, 1995, 66 (17) :2206-2208

[5] POLARITY ASYMMETRY OF OXIDES GROWN ON POLYCRYSTALLINE SILICON [J].

LEE, JC ;

HU, CM .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 1988, 35 (07) :1063-1070

[6]

LEE JW, P MAT RES SOC 1995 S, P441

[7] HIGH-PERFORMANCE LOW-TEMPERATURE POLYSILICON THIN-FILM-TRANSISTOR USING ECR PLASMA THERMAL OXIDE AS GATE INSULATOR [J].

LEE, JY ;

HAN, CH ;

KIM, CK .

IEEE ELECTRON DEVICE LETTERS, 1994, 15 (08) :301-303

[8] Thickness scaling limitation factors of ONO interpoly dielectric for nonvolatile memory devices [J].

Mori, S ;

Araki, YY ;

Sato, M ;

Meguro, H ;

Tsunoda, H ;

Kamiya, E ;

Yoshikawa, K ;

Arai, N ;

Sakagami, E .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 1996, 43 (01) :47-53

[9] ELECTRICAL CHARACTERISTICS OF TEXTURED POLYSILICON OXIDE PREPARED BY A LOW-TEMPERATURE WAFER LOADING AND N-2 PREANNEALING PROCESS [J].

WU, SL ;

LIN, TY ;

LEE, CL ;

LEI, TF .

IEEE ELECTRON DEVICE LETTERS, 1993, 14 (03) :113-114

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