Four-layer resist process for asymmetric gate recess

被引:6
作者
Grundbacher, R
Youtsey, C
Adesida, I
机构
[1] Ctr. Compd. Semiconduct. M., Coordinated Science Laboratory, University of Illinois, Urbana, IL 61801
基金
美国国家科学基金会;
关键词
D O I
10.1016/0167-9317(95)00254-5
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In this paper, we present an optimized four-layer resist (PMMA and its copolymers) process for the fabrication of T-shaped gates used in compound semiconductor field effect transistors (FETs). The process is capable of producing a profile which acts as both the etch mask for the wide, asymmetric recess trench as well as the liftoff mask for a T-shaped gate metal. The resist profile is achieved in a single step using electron beam lithography, eliminating the need for two separate lithography steps and the crucial alignment between them. Gate lengths of 100 mm are achieved using this process. Recess widths on the drain side of the gate range from 50 to 300 nn, and recess widths on the source side of the gate are 50 nm.
引用
收藏
页码:317 / 320
页数:4
相关论文
共 6 条
[1]   MULTILAYER RESIST PROCESS FOR ASYMMETRIC GATE RECESS IN FIELD-EFFECT TRANSISTORS [J].
BALLEGEER, DG ;
NUMMILA, K ;
ADESIDA, I .
JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B, 1993, 11 (06) :2560-2564
[2]   INALAS/INGAAS/INP HEMTS WITH HIGH BREAKDOWN VOLTAGES USING DOUBLE-RECESS GATE PROCESS [J].
BOOS, JB ;
KRUPPA, W .
ELECTRONICS LETTERS, 1991, 27 (21) :1909-1910
[3]   TWO-DIMENSIONAL SIMULATION OF SUBMICROMETER GAAS-MESFETS - SURFACE EFFECTS AND OPTIMIZATION OF RECESSED GATE STRUCTURES [J].
HELIODORE, F ;
LEFEBVRE, M ;
SALMER, G ;
ELSAYED, OL .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1988, 35 (07) :824-830
[4]   EXTREMELY HIGH-GAIN 0.15-MU-M GATE-LENGTH INALAS/INGAAS/INP HEMTS [J].
HO, P ;
KAO, MY ;
CHAO, PC ;
DUH, KHG ;
BALLINGALL, JM ;
ALLEN, ST ;
TESSMER, AJ ;
SMITH, PM .
ELECTRONICS LETTERS, 1991, 27 (04) :325-327
[5]   BIAS DEPENDENCE OF THE MODFET INTRINSIC MODEL ELEMENTS VALUES AT MICROWAVE-FREQUENCIES [J].
HUGHES, B ;
TASKER, PJ .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1989, 36 (10) :2267-2273
[6]   LOW-CONDUCTANCE DRAIN (LCD) DESIGN OF INALAS/INGAAS/INP HEMTS [J].
PAO, YC ;
HARRIS, JS .
IEEE ELECTRON DEVICE LETTERS, 1992, 13 (10) :535-537