Investigation of gate to contact spacing effect on ESD robustness of salicided deep submicron single finger NMOS transistors

ESD failure threshold of NMOS transistors is known to degrade with the use of silicided diffusions owing to insufficient ballast resistance, making them susceptible to current localization, which leads to early ESD failure. It is commonly believed that the gate-to-contact spacing of silicided devices has no impact on the ESD strength. However, experimental results presented in this paper show that the ESD strength depends on the gate-to-contact spacing independent of the silicided process. This paper also presents results of a detailed investigation of the influence of gate-to-source and gate-to-drain contact spacings for a salicided 0.13 mum technology and provides new insight into the behavior of ESD protection devices. It is shown that the reduction in current localization and increase in the power dissipating volume with increase in the gate-to-contact spacings are root causes of this improvement, which implies that even for silicided processes, the gate-to-contact spacing should be carefully considered for efficient and robust ESD protection designs.