Determination of the interface trap density of rubrene single-crystal field-effect transistors and comparison to the bulk trap density

In order to gain further insight into the details of charge transport in organic semiconductor devices it is necessary to characterize the density of trap states at the semiconductor/gate dielectric interface. Here we use the technique of gate bias stress to quantitatively determine the interface trap density in rubrene single-crystal field-effect transistors with two different types of interfaces. A reversible and reproducible shift of the I-V characteristics is observed upon both negative and positive gate bias stress, whose physical origin is identified as charge trapping and detrapping at the crystal/SiO2 insulator interface. We can thus quantify the density of interface traps that are alternately filled and emptied on a time scale of congruent to 1 h in the energy range defined by the applied bias stress. For a typical rubrene/SiO2 interface we extract a density of similar to 2x10(12) cm(-2) at a stress bias of +/- 50 V, corresponding to a volume density of congruent to 10(19)/(cm(3) eV). An octadecyltrichlorosilane treatment of the SiO2 dielectric surface reduced this charge density by more than a factor of 2. The bulk trap density derived from space-charge-limited current measurements is typically three orders of magnitude lower, highlighting the dominant role in charge trapping played by the crystal/dielectric interface. (c) 2006 American Institute of Physics.