Surface passivation technology for III-V semiconductor nanoelectronics

被引:48
作者
Hasegawa, Hideki [1 ]
Akazawa, Masamichi
机构
[1] Hokkaido Univ, Res Ctr Integrated Quantum Elect RCIQE, Kita Ku, Sapporo, Hokkaido 0608628, Japan
关键词
III-V Semiconductor; Surface passivation; Nanoelectronics; MOS structure; High-k dielectric; GaAs;
D O I
10.1016/j.apsusc.2008.07.002
中图分类号
O64 [物理化学(理论化学)、化学物理学];
学科分类号
070304 ; 081704 ;
摘要
The present status and key issues of surface passivation technology for III-V surfaces are discussed in view of applications to emerging novel III-V nanoelectronics. First, necessities of passivation and currently available surface passivation technologies for GaAs, InGaAs and AlGaAs are reviewed. Then, the principle of the Si interface control layer (ICL)-based passivation scheme by the authors' group is introduced and its basic characterization is presented. Ths Si ICL is a molecular beam epitaxy ( MBE)grown ultrathin Si layer inserted between III-V semiconductor and passivation dielectric. Finally, applications of the Si ICL method to passivation of GaAs nanowires and GaAs nanowire transistors and to realization of pinning-free high-k dielectric/GaAs MOS gate stacks are presented. (c) 2008 Elsevier B. V. All rights reserved.
引用
收藏
页码:628 / 632
页数:5
相关论文
共 44 条
[1]   Formation of ultrathin SiNx/Si interface control double layer on (001) and (111) GaAs surfaces for ex situ,deposition of high-k dielectrics [J].
Akazawa, Masamichi ;
Hasegawa, Hideki .
JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B, 2007, 25 (04) :1481-1490
[2]   MBE growth and in situ XPS characterization of silicon interlayers on (111)B surfaces for passivation of GaAs quantum wire devices [J].
Akazawa, Masamichi ;
Hasegawa, Hideki .
JOURNAL OF CRYSTAL GROWTH, 2007, 301 :951-954
[3]   Pinning-free GaAs MIS structures with Si interface control layers formed on (4 x 6) reconstructed (001) surface [J].
Anantathanasarn, S ;
Hasegawa, H .
APPLIED SURFACE SCIENCE, 2003, 216 (1-4) :275-282
[4]   Microwave performance of GaAs MOSFET with wet thermally oxidized InAlP gate dielectric [J].
Cao, Y. ;
Li, X. ;
Zhang, J. ;
Fay, P. ;
Kosel, T. H. ;
Hall, D. C. .
IEEE ELECTRON DEVICE LETTERS, 2006, 27 (05) :317-319
[5]   Benchmarking nanotechnology for high-performance and low-power logic transistor applications [J].
Chau, R ;
Datta, S ;
Doczy, M ;
Doyle, B ;
Jin, J ;
Kavalieros, J ;
Majumdar, A ;
Metz, M ;
Radosavljevic, M .
IEEE TRANSACTIONS ON NANOTECHNOLOGY, 2005, 4 (02) :153-158
[6]  
CHAU R, 2006, IEEE DEV RES C U PAR, V3
[7]   GAAS MIS STRUCTURES WITH SIO2 USING A THIN SILICON INTERLAYER [J].
FOUNTAIN, GG ;
HATTANGADY, SV ;
VITKAVAGE, DJ ;
RUDDER, RA ;
MARKUNAS, RJ .
ELECTRONICS LETTERS, 1988, 24 (18) :1134-1135
[8]   TIGHT-BINDING THEORY OF HETEROJUNCTION BAND LINEUPS AND INTERFACE DIPOLES [J].
HARRISON, WA ;
TERSOFF, J .
JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B, 1986, 4 (04) :1068-1073
[9]   Formation of III-V low dimensional structures and their applications to intelligent quantum chips [J].
Hasegawa, H .
MICROELECTRONICS JOURNAL, 2003, 34 (5-8) :341-345
[10]   Effects of gap states an scanning tunneling spectra observed on (110)- and (001)-oriented clean surfaces and ultrathin Si layer covered surfaces of GaAs prepared by molecular beam epitaxy [J].
Hasegawa, H ;
Negoro, N ;
Kasai, S ;
Ishikawa, Y ;
Fujikuwa, H .
JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B, 2000, 18 (04) :2100-2108