Surface passivation technology for III-V semiconductor nanoelectronics

被引：48

作者：

Hasegawa, Hideki ^{[1
]}

Akazawa, Masamichi

机构：

[1] Hokkaido Univ, Res Ctr Integrated Quantum Elect RCIQE, Kita Ku, Sapporo, Hokkaido 0608628, Japan

来源：

APPLIED SURFACE SCIENCE | 2008年 / 255卷 / 03期

关键词：

III-V Semiconductor; Surface passivation; Nanoelectronics; MOS structure; High-k dielectric; GaAs;

D O I：

10.1016/j.apsusc.2008.07.002

中图分类号：

O64 [物理化学（理论化学）、化学物理学];

学科分类号：

070304 ; 081704 ;

摘要：

The present status and key issues of surface passivation technology for III-V surfaces are discussed in view of applications to emerging novel III-V nanoelectronics. First, necessities of passivation and currently available surface passivation technologies for GaAs, InGaAs and AlGaAs are reviewed. Then, the principle of the Si interface control layer (ICL)-based passivation scheme by the authors' group is introduced and its basic characterization is presented. Ths Si ICL is a molecular beam epitaxy ( MBE)grown ultrathin Si layer inserted between III-V semiconductor and passivation dielectric. Finally, applications of the Si ICL method to passivation of GaAs nanowires and GaAs nanowire transistors and to realization of pinning-free high-k dielectric/GaAs MOS gate stacks are presented. (c) 2008 Elsevier B. V. All rights reserved.

引用

页码：628 / 632

页数：5

共 44 条

[1] Formation of ultrathin SiNx/Si interface control double layer on (001) and (111) GaAs surfaces for ex situ,deposition of high-k dielectrics [J].