Logic performance of 40 nm InAsHEMTs

被引:53
作者
Kim, Dae-Hyun [1 ]
del Alamo, Jesus A. [1 ]
机构
[1] MIT, Cambridge, MA 02139 USA
来源
2007 IEEE INTERNATIONAL ELECTRON DEVICES MEETING, VOLS 1 AND 2 | 2007年
关键词
D O I
10.1109/IEDM.2007.4419018
中图分类号
T [工业技术];
学科分类号
08 ;
摘要
We have experimentally evaluated the logic performance of 40 nm InAs HEMTs. For a barrier thickness of 4 nm, we find that 40 nm InAs HEMTs exhibit excellent logic figures of merit and scalability at VDS = 0.5 V, such as DIBL = 80 mV/V, S = 70 mV/dec., and f(T) = 475 GHz. These remarkable results arise from the combination of the outstanding transport properties of InAs channel, and the use of a thin insulator and a thin channel. In addition, these devices exhibit I-ON/I-OFF ratios in excess of 104, revealing that band-to-band tunneling is not a significant concern in our device design. Our InAs HEMTs exhibit an injection velocity at the virtual source point that is a factor of 1.6X higher than state-of-the-art Si n-MOSFETs, in spite of the significantly lower supply voltage.
引用
收藏
页码:629 / 632
页数:4
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