Logic suitability of 50-nm In0.7Ga0.3AsHEMTs for Beyond-CMOS applications

We have experimentally studied the suitability of nanometer-scale In0.7Ga0.3As high-electron mobility transistors (HEMTs) as an n-channel device for a future high-speed and low-power logic technology for beyond-CMOS applications. To this end, we have fabricated 50- to 150-nm-gate-length In0.7Ga0.3As HEMTs with different gate stack designs. This has allowed us to investigate the role of Schottky barrier height (Phi(B)) and insulator thickness (t(ins).) on the logic characteristics of In0.7Ga0.3As HEMTs. The best 50-nm HEMTs with the highest I B and the smallest T-ins exhibit an I-ON/I-OFF ratio in excess of 104 and a subthreshold slope (S) below 86 mV/dec. These nonoptimized 50-nm In0.7Ga0.3As HEMTs also show a logic gate delay (CV/I) of around 1 ps at a supply voltage of 0.5 V, while maintaining an ION/IOFF ratio above 104, which is comparable to state-of-the-art Si MOSFETs. As one of the alternatives for beyond-CMOS technologies, we believe that InAs-rich InGaAs HENTs hold a considerable promise.