InP-based high electron mobility transistors with a very short gate-channel distance

被引:39
作者
Endoh, A
Yamashita, Y
Shinohara, K
Hikosaka, K
Matsui, T
Hiyamizu, S
Mimura, T
机构
[1] Fujitsu Labs Ltd, Atsugi, Kanagawa 2430197, Japan
[2] Osaka Univ, Grad Sch Engn Sci, Toyonaka, Osaka 5608531, Japan
[3] Commun Res Labs, Koganei, Tokyo 1848795, Japan
来源
JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS | 2003年 / 42卷 / 4B期
关键词
high electron mobility transistor; HEMT; InAlAs/InGaAs; InP; cutoff frequency; lattice-matched; pseudomorphic; gate-channel distance; two-step-recessed gate; Monte Carlo simulation;
D O I
10.1143/JJAP.42.2214
中图分类号
O59 [应用物理学];
学科分类号
摘要
We fabricated 25-nm-gate lattice-matched InAlAs/InGaAs high electron mobility transistors (HEMTs) with a very short gate-channel distance. Using the two-step-recessed gate technique, we reduced the gate-channel distance to 4 nm; We found that the cutoff frequency f(T) increases with decreasing gate-channel distance d. This phenomenon can be explained by an increase in electron velocity under the gate with decreasing d. We obtained an f(T) of 500 GHz with a d of 4 nm. We also fabricated 25-nm-gate pseudomorphic In0.52Al0.48As/In0.7Ga0.3As HEMTs using the same processing technique, and obtained an f(T) of 562 GHz with a d of 4 nm. This f(T) is the highest value yet reported for a transistor of any type.
引用
收藏
页码:2214 / 2218
页数:5
相关论文
共 16 条
[1]   SHORT-CHANNEL EFFECTS IN SUBQUARTER-MICROMETER-GATE HEMTS - SIMULATION AND EXPERIMENT [J].
AWANO, Y ;
KOSUGI, M ;
KOSEMURA, K ;
MIMURA, T ;
ABE, M .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1989, 36 (10) :2260-2266
[2]   ELIMINATION OF MESA-SIDEWALL GATE LEAKAGE IN INA1AS/INGAAS HETEROSTRUCTURES BY SELECTIVE SIDEWALL RECESSING [J].
BAHL, SR ;
DELALAMO, JA .
IEEE ELECTRON DEVICE LETTERS, 1992, 13 (04) :195-197
[3]   A NEW METHOD FOR DETERMINING THE FET SMALL-SIGNAL EQUIVALENT-CIRCUIT [J].
DAMBRINE, G ;
CAPPY, A ;
HELIODORE, F ;
PLAYEZ, E .
IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, 1988, 36 (07) :1151-1159
[4]   Fabrication technology and device performance of sub-50-nm-gate InP-based high electron mobility transistors [J].
Endoh, A ;
Yamashita, Y ;
Shinohara, K ;
Higashiwaki, M ;
Hikosaka, K ;
Mimura, T ;
Hiyamizu, S ;
Matsui, T .
JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS, 2002, 41 (2B) :1094-1098
[5]  
Endoh A, 2001, IEICE T ELECTRON, VE84C, P1328
[6]  
ENDOH A, UNPUB
[7]   DELAY TIME ANALYSIS FOR 0.4-MUM TO 5-MUM-GATE INALAS-INGAAS HEMTS [J].
ENOKI, T ;
ARAI, K ;
ISHII, Y .
IEEE ELECTRON DEVICE LETTERS, 1990, 11 (11) :502-504
[8]   Extremely high-speed lattice-matched InGaAs/InAlAs high electron mobility transistors with 472 GHz cutoff frequency [J].
Shinohara, K ;
Yamashita, Y ;
Endoh, A ;
Hikosaka, K ;
Matsui, T ;
Mimura, T ;
Hiyamizu, S .
JAPANESE JOURNAL OF APPLIED PHYSICS PART 2-LETTERS & EXPRESS LETTERS, 2002, 41 (4B) :L437-L439
[9]   Ultrahigh-speed pseudomorphic InGaAs/InAlAs HEMTs with 400-GHz cutoff frequency [J].
Shinohara, K ;
Yamashita, Y ;
Endoh, A ;
Hikosaka, K ;
Matsui, T ;
Mimura, T ;
Hiyamizu, S .
IEEE ELECTRON DEVICE LETTERS, 2001, 22 (11) :507-509
[10]  
Shinohara K., 2000, P GALL ARS OTH SEM A, P252