The impact of side-recess spacing on the logic performance of 50 nm In0.7Ga0.3AsHEMTs

We are investigating InGaAs HEMTs as a future high-speed, low-power logic technology for beyond CMOS applications. In thus work we have experimentally studied the role of the siderecess spacing (L-side) on the logic performance of 50nm In0.7Ga0.3As HEMTs. We have found that L-side has a large impact on electrostatic integrity (short chattel effects), gate leakage current, gate-drain capacitance, and source and drain resistance. For our device design, an optimum value of L-side of 150 nn is found. 50 run In0.7Ga0.3As HEMTs with thus value of L-side exhibit I-ON/I-OFF ratios in excess of 10(4), subthreshold slopes smaller than 90 mV/dec. and logic gate delays of about 1.3 ps at a V-cc of '0.5 V. In spite of the fact that these devices are not optimized for logic, these values are comparable to state-of-the-art MOSFETs of similar gate lengths. Our work shows that in the landscape of alternatives for beyond CMOS technologies, InAs-rich InGaAs HEMTs hold considerable promise.