共 36 条
[22]
Lisman J., 2010, FRONTIERS SYNAPTIC N, V2
[23]
A current-mode conductance-based silicon neuron for Address-Event neuromorphic systems
[J].
ISCAS: 2009 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-5,
2009,
:2898-+
[24]
Modha D., 2010, U.S. Patent, Patent No. [20 100 299 296, 20100299296]
[25]
Pellizzer F., 2006, S VLSI TECHNOL DIG T, P122, DOI [10.1109/VLSIT.2006.1705247, DOI 10.1109/VLSIT.2006.1705247]
[26]
Self-aligned μTrench Phase-Change Memory cell architecture for 90nm technology and beyond
[J].
ESSDERC 2007: PROCEEDINGS OF THE 37TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE,
2007,
:222-+
[27]
Querlioz D., 2011, 2011 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), P150, DOI 10.1109/NANOARCH.2011.5941497
[28]
Querlioz D, 2011, 2011 INTERNATIONAL JOINT CONFERENCE ON NEURAL NETWORKS (IJCNN), P1775, DOI 10.1109/IJCNN.2011.6033439
[29]
Sasago Y, 2009, 2009 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, P24
[30]
Spike-timing-dependent learning in memristive nanodevices
[J].
2008 IEEE INTERNATIONAL SYMPOSIUM ON NANOSCALE ARCHITECTURES,
2008,
:85-92