Physically-based threshold voltage determination for MOSFET's of all gate lengths

被引：90

作者：

Tsuno, M ^{[1
]}

Suga, M ^{[1
]}

Tanaka, M ^{[1
]}

Shibahara, K ^{[1
]}

Miura-Mattausch, M ^{[1
]}

Hirose, M ^{[1
]}

机构：

[1] Hiroshima Univ, Res Ctr Nanodevices & Syst, Dept Engn, Higashihiroshima 7398527, Japan

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 1999年 / 46卷 / 07期

关键词：

D O I：

10.1109/16.772487

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A reliable method to determine the threshold voltage V-th for MOSFET's with gate length down to the sub-0.1 mu m region is proposed. The method determines V-th by linear extrapolation of the transconductance g(m) to zero and is therefore named "GMLE method." To understand the physical meaning of the method and to prove its reliability for different technologies 2-D simulation was applied. The results reveal that determined V-th values always meet the threshold condition, i.e., the onset of inversion layer buildup.

引用

页码：1429 / 1434

页数：6

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