Composition and growth kinetics of the interfacial layer for MOCVD HfO2 layers on Si substrates

被引:25
作者
Van Elshocht, S [1 ]
Caymax, M
De Gendt, S
Conard, T
Pétry, J
Daté, L
Pique, D
Heyns, MM
机构
[1] IMEC VZW, Heverlee, Belgium
[2] Appl Mat France, Meylan, France
关键词
D O I
10.1149/1.1648027
中图分类号
O646 [电化学、电解、磁化学];
学科分类号
081704 ;
摘要
To boost MOS transistor performance, thickness of the gate dielectric is continuously scaled down. This results in an increase of gate tunneling leakage current, which at some point prevents further downscaling. Desired parameters of alternative materials to SiO2 are a higher dielectric constant (high-k materials), stability, and compatibility with silicon. A general observation for one of the prime candidates, HfO2, is formation of an interfacial layer between the silicon and the high-k material that limits scalability because of its low k-value. Hence, a thorough study of the formation of this layer and its contribution to the equivalent oxide thickness is of utmost importance. We studied the composition and growth kinetics of the interfacial layer formed during the deposition of HfO2 by metallorganic chemical vapor deposition using O-2 and tetrakis-diethylamidohafnium as precursor. We found the composition and thickness of the interfacial layer to be dependent on the deposition parameters as well as on the starting surface. The layer's composition is hafnium silicate-like and its thickness increases as a function of deposition time and temperature. It is therefore controlled by deposition of the HfO2 layer. (C) 2004 The Electrochemical Society.
引用
收藏
页码:F77 / F80
页数:4
相关论文
共 17 条
[1]   THEORY OF THE OXIDATION OF METALS [J].
CABRERA, N ;
MOTT, NF .
REPORTS ON PROGRESS IN PHYSICS, 1948, 12 :163-184
[2]   Open-circuit potential analysis as a fast screening method for the quality of high-k dielectric layers [J].
Claes, M ;
Witters, T ;
Loriaux, G ;
Van Elshocht, S ;
Delabie, A ;
De Gendt, S ;
Heyns, MM ;
Okorn-Schmidt, H .
ULTRA CLEAN PROCESSING OF SILICON SURFACES V, 2003, 92 :7-10
[3]  
Cumpson PJ, 1997, SURF INTERFACE ANAL, V25, P430, DOI 10.1002/(SICI)1096-9918(199706)25:6<430::AID-SIA254>3.0.CO
[4]  
2-7
[5]   GENERAL RELATIONSHIP FOR THERMAL OXIDATION OF SILICON [J].
DEAL, BE ;
GROVE, AS .
JOURNAL OF APPLIED PHYSICS, 1965, 36 (12) :3770-&
[6]  
FEHNLER FP, 1970, OXID MET, V2, P59
[7]   Modeling of Si 2p core-level shifts at Si-(ZrO2)x(SiO2)1-x interfaces [J].
Giustino, F ;
Bongiorno, A ;
Pasquarello, A .
APPLIED PHYSICS LETTERS, 2002, 81 (22) :4233-4235
[8]   Nucleation and growth of atomic layer deposited HfO2 gate dielectric layers on chemical oxide (Si-O-H) and thermal oxide (SiO2 or Si-O-N) underlayers [J].
Green, ML ;
Ho, MY ;
Busch, B ;
Wilk, GD ;
Sorsch, T ;
Conard, T ;
Brijs, B ;
Vandervorst, W ;
Räisänen, PI ;
Muller, D ;
Bude, M ;
Grazul, J .
JOURNAL OF APPLIED PHYSICS, 2002, 92 (12) :7168-7174
[9]  
HEYNS MM, 1993, MATER RES SOC SYMP P, V315, P35, DOI 10.1557/PROC-315-35
[10]   Sub-quarter micron Si-gate CMOS with ZrO2 gate dielectric [J].
Hobbs, C ;
Dip, L ;
Reid, K ;
Gilmer, D ;
Hegde, R ;
Ma, T ;
Taylor, B ;
Cheng, B ;
Samavedam, S ;
Tseng, H ;
Weddington, D ;
Huang, F ;
Farber, D ;
Schippers, M ;
Rendon, M ;
Prabhu, L ;
Rai, R ;
Bagchi, S ;
Conner, J ;
Backer, S ;
Dumbuya, F ;
Locke, J ;
Workman, D ;
Tobin, P .
2001 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS, AND APPLICATIONS, PROCEEDINGS OF TECHNICAL PAPERS, 2001, :204-207