Investigation of electrical characteristics on surrounding-gate and omega-shaped-gate nanowire FinFETs

被引：89

作者：

Li, YM ^{[1
]}

Chou, HM

Lee, JW

机构：

[1] Natl Chiao Tung Univ, Dept Commun Engn, Hsinchu 300, Taiwan

[2] Natl Chiao Tung Univ, Microelect & Informat Syst Res Ctr, Hsinchu 300, Taiwan

来源：

IEEE TRANSACTIONS ON NANOTECHNOLOGY | 2005年 / 4卷 / 05期

关键词：

coverage ratio; device structure; fabrication; fin field-effect transistor (FinFET); gate capacitance; nanodevice; nanowire; omega-shaped-gate; on/off ratio; process technique; quantum correction model; semiconductor devices; subthreshold swing (SS); surrounding gate; three-dimensional (3-D) simulation; turn-on resistance;

D O I：

10.1109/TNANO.2005.851410

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, electrical characteristics of small nanowire fin field-effect transistor (FinFET) are investigated by using a three-dimensional quantum correction simulation. Taking several important electrical characteristics as evaluation criteria, two different nanowire FinFETs, the surrounding-gate and omega-shaped-gate devices, are examined and compared with respect to different ratios of the gate coverage. By calculating the ratio of the on/off current, the turn-on resistance, subthreshold swing, drain-induced channel barrier height lowing, and gate capacitance, it is found that the difference of the electrical characteristics between the surrounding-gate (i.e., the omega-shaped-gate device with 100% coverage) and the omega-shaped-gate nanowire FinFET with 70% coverage is insignificant. The examination presented here is useful in the fabrication of small omega-shaped-gate nanowire FinFETs. It clarifies the main difference between the surrounding-gate and omega-shaped-gate nanowire Fin FETs and exhibits a valuable result that the omega-shaped-gate device with 70% coverage plays an optimal candidate of the nanodevice structure when we consider both the device performance and manufacturability.

引用

页码：510 / 516

页数：7

共 61 条

[31]

MAJIMA H, 2001, IEEE INT EL DEV M IE, P951

[32] 50nm-gate all around (GAA) - Silicon on nothing (SON) - Devices: A simple way to co-integration of GAA transistors within bulk MOSFET process [J].

Monfray, S ;

Skotnicki, T ;

Morand, Y ;

Descombes, S ;

Coronel, P ;

Mazoyer, P ;

Harrison, S ;

Ribot, P ;

Talbot, A ;

Dutartre, D ;

Haond, M ;

Palla, R ;

Le Friec, Y ;

Leverd, F ;

Nier, ME ;

Vizioz, C ;

Louis, D .

2002 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, 2002, :108-109

[33] Modeling of 10-nm-scale ballistic MOSFET's [J].

Naveh, Y ;

Likharev, KK .

IEEE ELECTRON DEVICE LETTERS, 2000, 21 (05) :242-244

[34] Integration challenges of new materials and device Architectures for IC applications [J].

Nguyen, BY ;

Thean, A ;

White, T ;

Vandooren, A ;

Sadaka, M ;

Mathew, L ;

Barr, A ;

Thomas, S ;

Zalava, M ;

Da Zhang ;

Eades, D ;

Shi, ZH ;

Schaeffer, J ;

Triyoso, D ;

Samavedam, S ;

Vartanian, V ;

Stephen, T ;

Goolsby, B ;

Zollner, S ;

Liu, R ;

Noble, R ;

Nguyen, T ;

Dhandapani, V ;

Xie, B ;

Wang, XD ;

Jiang, J ;

Rai, R ;

Sadd, M ;

Ramon, M ;

Kalpat, S ;

Prabhu, L ;

Kaushik, V ;

Du, Y ;

Dao, T ;

Mendicino, M ;

Orlowski, M ;

Tobin, P ;

Mogab, J ;

Venkatesan, S .

2004 INTERNATIONAL CONFERENCE ON INTEGRATED CIRCUIT DESIGN AND TECHNOLOGY, 2004, :237-243

[35] Multidimensional discretization of the stationary quantum drift-diffusion model for ultrasmall MOSFET structures [J].

Odanaka, S .

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2004, 23 (06) :837-842

[36]

Ogawa M, 2002, SISPAD 2002: INTERNATIONAL CONFERENCE ON SIMULATION OF SEMICONDUCTOR PROCESSES AND DEVICES, P261, DOI 10.1109/SISPAD.2002.1034568

[37] Multiple-gate SOI MOSFETs: Device design guidelines [J].

Park, JT ;

Colinge, JP .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 2002, 49 (12) :2222-2229

[38] Pi-gate SOI MOSFET [J].

Park, JT ;

Colinge, JP ;

Diaz, CH .

IEEE ELECTRON DEVICE LETTERS, 2001, 22 (08) :405-406

[39]

PARK T, 2003, P DRC SALT LAK CIT U, P33

[40] A numerical study of ballistic transport in a nanoscale MOSFET [J].

Rhew, JH ;

Ren, ZB ;

Lundstrom, MS .

SOLID-STATE ELECTRONICS, 2002, 46 (11) :1899-1906

← 1 2 3 4 5 6 7 →