Contribution of fast and slow states to Negative Bias Temperature Instabilities in HfxSi(1-x)ON/TaN based pMOSFETs

Fast and slow states contributions to threshold voltage shifts of HfSiON/TaN gate stacks under negative bias temperature (NBT) stress are investigated. Fast states contribution to the total defects produced ranges between about 20 and 50%, depending on stress bias and temperature. The time and temperature dependence of the fast states is consistent with the reaction-diffusion model, while the kinetics and temperature dependence of the slow states suggest the production of hole traps in the bulk of the gate dielectric stack. Fast and slow states are recovered when the NBT stress is interrupted, the fraction of slow states recovered being larger by a factor about 2.