Device scaling limits of Si MOSFETs and their application dependencies

被引:1078
作者
Frank, DJ [1 ]
Dennard, RH [1 ]
Nowak, E [1 ]
Solomon, PM [1 ]
Taur, Y [1 ]
Wong, HSP [1 ]
机构
[1] IBM Corp, Thomas J Watson Res Ctr, Yorktown Hts, NY 10598 USA
关键词
CMOS; device design; discrete dopants; double-gate MOSFET; DRAM; high-K dielectrics; high-performance logic; leakage currents; limits; low power; MOSFET; nanotechnology;
D O I
10.1109/5.915374
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper presents the current state of understanding of the factors that limit the continued scaling of Si complementary metal-oxide-semiconductor (CMOS) technology and prov ides an analysis of the ways in which application-related considerations enter into the determination of these limits. The physical origins of these limits are primarily in the tunneling currents. which leak through the various barriers in a MOS field-effect transistor (MOSFET) when it becomes very small. and in the thermally generated subthreshold currents. The dependence of these leakages on MOSFET geometry? and structure is discussed along with design criteria for minimizing short-channel effects and other issues related to scaling. Scaling limits due to these leakage currents arise from application constraints related to power consumption and circuit functionality. We describe her; these constraints work out for some of the most important application classes: dynamic random access memory (DRAM, static random access memory (SRAM), low-power portable det ices, and moderate and high-performance CMOS logic. As a summary: we provide a table of our estimates of the scaling limits for various applications and device types. The end result is that there is no single end point for scaling. but that instead there are many end points, each optimally adapted to its particular applications.
引用
收藏
页码:259 / 288
页数:30
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