Monitoring interface traps by DCIV method

被引:41
作者
Cai, J
Sah, CT
机构
[1] Florida Solid-State Electronics Laboratory, Department of Electrical and Computer Engineering, University of Florida, Gainesville
关键词
Charge carrier processes; MOSFET's; reliability; semiconductor-insulator interfaces;
D O I
10.1109/55.737574
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
DCIV method is demonstrated as a production monitoring tool for process-residue interface traps. The high sensitivity of the methodology attained from forward-biasing an pin junction allows routine detection of as few as 100 active interface traps in small area MOS transistors, Examples are given for MOST's from five different sub-half-micron production technologies. The body recombination current shows peaks around the intrinsic surface condition whose amplitude is proportional to the number of active interface traps in the mid-channel region, The variation of the peak amplitude with the forward bias voltage follows exactly the single-energy level formula, from which the interface-trap energy level can be determined to a few tenths of a kT accuracy.
引用
收藏
页码:60 / 63
页数:4
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