Profiling interface traps in MOS transistors by the DC current-voltage method

Position profiling the interface trap density along the channel length of metal-oxide-silicon transistors by the Direct-Current Current-Voltage method is illustrated for five density variations: zero, peaked in drain junction space-charge layer, constant in channel, nonconstant in channel, and peaked in drain junction space-charge layer and nonconstant in channel, The interface trap densities were monitored by MOS transistor's d.c. body current and the density profiles were obtained from the body-drain and body-source differential conductance versus drain or source bias voltage, An experimental demonstration is given for a 1.6 mu m n-channel Si MOS transistor with about 10(11) traps/cm(2) generated by channel hot electron stress.