Trade-offs in the design of a router with both guaranteed and best-effort services for networks on chip

被引:178
作者
Rijpkema, E [1 ]
Goossens, K [1 ]
Radulescu, A [1 ]
Dielissen, J [1 ]
van Meerbergen, J [1 ]
Wielage, P [1 ]
Waterlander, E [1 ]
机构
[1] Philips Res Labs, Eindhoven, Netherlands
来源
IEE PROCEEDINGS-COMPUTERS AND DIGITAL TECHNIQUES | 2003年 / 150卷 / 05期
关键词
D O I
10.1049/ip-cdt:20030830
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Managing the complexity of designing chips containing billions of transistors requires decoupling computation from communication. For the communication, scalable and compositional interconnects, such as networks on chip (NoC), must be used. It is shown that guaranteed services are essential in achieving this decoupling. Guarantees typically come at the cost of lower resource utilisation. To avoid this, they must be used in combination with best-effort services. The key element of this NoC is a router consisting conceptually of two parts; the so-called guaranteed-throughput (GT) and best-effort (BE) routers. The GT and BE router architectures are combined in an efficient implementation by sharing resources. The trade-offs between hardware complexity and efficiency of the combined router are shown that motivate the choices. The reasoning for the trade-offs is validated with a prototype router implementation. A layout is shown of an input-queued wormhole 5 x 5 router with an aggregate bandwidth of 80 Gbit/s. It occupies 0.26 mm(2) in a 0.13 mum technology. This shows that our router provides high performance at-reasonable cost, bringing NoCs one step closer.
引用
收藏
页码:294 / 302
页数:9
相关论文
共 19 条
  • [1] ALI MKM, 1991, P JOINT C IEEE COMP, V2, P454
  • [2] Chain: A delay-insensitive chip area interconnect
    Bainbridge, J
    Furber, S
    [J]. IEEE MICRO, 2002, 22 (05) : 16 - 23
  • [3] Powering networks on chips - Energy-efficient and reliable interconnect design for SoCs
    Benini, L
    De Micheli, G
    [J]. ISSS'01: 14TH INTERNATIONAL SYMPOSIUM ON SYSTEM SYNTHESIS, 2001, : 33 - 38
  • [4] Networks on chips: A new SoC paradigm
    Benini, L
    De Micheli, G
    [J]. COMPUTER, 2002, 35 (01) : 70 - +
  • [5] Dally WJ, 2001, DES AUT CON, P684, DOI 10.1109/DAC.2001.935594
  • [6] DEHON A, 1993, 1445 MIT ART INT LAB
  • [7] Goossens K, 2003, NETWORKS ON CHIP, P61
  • [8] Networks on silicon: Combining best-effort and guaranteed services
    Goossens, K
    van Meerbergen, J
    Peeters, A
    Wielage, P
    [J]. DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION, 2002 PROCEEDINGS, 2002, : 423 - 425
  • [9] Guerrier P., 2000, Proceedings Design, Automation and Test in Europe Conference and Exhibition 2000 (Cat. No. PR00537), P250, DOI 10.1109/DATE.2000.840047
  • [10] INPUT VERSUS OUTPUT QUEUING ON A SPACE-DIVISION PACKET SWITCH
    KAROL, MJ
    HLUCHYJ, MG
    MORGAN, SP
    [J]. IEEE TRANSACTIONS ON COMMUNICATIONS, 1987, 35 (12) : 1347 - 1356