New dynamic flip-flops for high-speed dual-modulus prescaler

被引：69

作者：

Yang, CY ^{[1
]}

Dehng, GK ^{[1
]}

Hsu, JM ^{[1
]}

Liu, SI ^{[1
]}

机构：

[1] Natl Taiwan Univ, Dept Elect Engn, Taipei 10664, Taiwan

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1998年 / 33卷 / 10期

关键词：

CMOS integrated circuits; flip-flops; high-speed circuits; prescaler;

D O I：

10.1109/4.720406

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A fast pipeline technique using single-phase, edge-triggered, ratioed, high-speed logic flip-flops and D hip-hops is introduced and analyzed. The circuits achieve high speed by reducing the capacitive load and sharing the delay between the combination logic blocks and the storage elements. By the way, it is suitable for realizing high-speed synchronous counters, A divide-by-128/129 and 64/65 dual-modulus prescaler using proposed hip-hops is measured in 0.8 mu m CMOS technology with the operating clock frequency reaching as high as 1.8 GHz.

引用

页码：1568 / 1571

页数：4

共 9 条

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