High performance high-k/metal gate ge pMOSFETs with gate lengths down to 125 nm and halo implant

被引：9

作者：

De Jaeger, B. ^{[1
,2
]}

Nicholas, G. ^{[1
]}

Brunco, D. P. ^{[3
]}

Eneman, G. ^{[1
,2
]}

Meuris, M. ^{[1
,2
]}

Heyns, M. M. ^{[1
,2
]}

机构：

[1] Sharp Labs, Oxford, England

[2] IMEC vzw, B-3001 Leuven, Belgium

[3] IMEC, Leuven, Belgium

来源：

ESSDERC 2007: PROCEEDINGS OF THE 37TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE | 2007年

关键词：

D O I：

10.1109/ESSDERC.2007.4430978

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Ge pMOSFETs with gate lengths down to 125 nm are fabricated in a Si-like process flow. The addition of a halo implant reduces V-T roll-off from 207 mV to 36 mV, and DIBL from 230 mV/V to 54 mV/V. I-ON of 770 mu A/mu m is attained for I-OFF of 8.8 nA/mu m at V-DD = -1.5 V, when evaluating from the source. Benchmarking shows these Ge pMOSFETs have the potential to outperform their (strained) Si counterparts. Measurements at 100 degrees C suggest that Ge will continue to be competitive at realistic logic operating temperatures.

引用

页码：462 / +

页数：2

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