High-Mobility Ge pMOSFET With 1-nm EOT Al2O3/GeOx/Ge Gate Stack Fabricated by Plasma Post Oxidation

被引:180
作者
Zhang, Rui [1 ]
Iwasaki, Takashi [1 ]
Taoka, Noriyuki [1 ]
Takenaka, Mitsuru [1 ]
Takagi, Shinichi [1 ]
机构
[1] Univ Tokyo, Sch Engn, Tokyo 1138656, Japan
关键词
Equivalent oxide thickness (EOT); germanium; metal-oxide-semiconductor field-effect transistor (MOSFET); mobility; INTERFACE; DENSITY;
D O I
10.1109/TED.2011.2176495
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
An ultrathin equivalent oxide thickness (EOT) Al2O3/GeOx/Ge gate stack with a superior GeOx/Ge metal-oxide-semiconductor (MOS) interface and p-channel metal-oxide-semiconductor field-effect transistors (pMOSFETs) using this gate stack have been fabricated by a plasma post oxidation method. The properties of the GeOx/Ge MOS interfaces are systemically investigated, and it is revealed that there is a universal relationship between the interface state density (D-it) at the GeOx/Ge interface and the GeOx interfacial layer thickness. Ge pMOSFETs on a (100) Ge substrate using the Al2O3/GeOx/Ge gate stack have been demonstrated with an EOT down to 0.98 nm. It is found that the Ge pMOSFETs exhibit the peak hole mobility values of 515, 466, and 401 cm(2)/V . s at an EOT of 1.18, 1.06, and 0.98 nm, respectively, which has much weaker EOT dependence than the trend of the hole mobility values reported so far, because of low D-it of the present gate stack in the ultrathin EOT region of similar to 1 nm.
引用
收藏
页码:335 / 341
页数:7
相关论文
共 23 条
[1]  
Bai W. P., 2003, 2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407), P121, DOI 10.1109/VLSIT.2003.1221115
[2]   RAPID INTERFACE PARAMETERIZATION USING A SINGLE MOS CONDUCTANCE CURVE [J].
BREWS, JR .
SOLID-STATE ELECTRONICS, 1983, 26 (08) :711-716
[3]  
Chui CO, 2002, IEEE ELECTR DEVICE L, V23, P473, DOI [10.1009/LED.2002.801319, 10.1109/LED.2002.801319]
[4]   Scalability and electrical properties of germanium oxynitride MOS dielectrics [J].
Chui, CO ;
Ito, F ;
Saraswat, KC .
IEEE ELECTRON DEVICE LETTERS, 2004, 25 (09) :613-615
[5]   Electrical analyses of germanium MIS structure and spectroscopic measurement of the interface trap density in an insulator/germanium interface at room temperature [J].
Fukuda, Yukio ;
Otani, Yohei ;
Itayarna, Yasuhiro ;
Ono, Toshiro .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2007, 54 (11) :2878-2883
[6]   High-k/Ge p- & n-MISFETs with Strontium Germanide Interlayer for EOT Scalable CMIS Application [J].
Kamata, Yoshiki ;
Ikeda, Keiji ;
Kamimuta, Yuuichi ;
Tezuka, Tsutomu .
2010 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, 2010, :211-212
[7]   Radical oxidation of germanium for interface gate dielectric GeO2 formation in metal-insulator-semiconductor gate stack [J].
Kobayashi, Masaharu ;
Thareja, Gaurav ;
Ishibashi, Masato ;
Sun, Yun ;
Griffin, Peter ;
McVittie, Jim ;
Pianetta, Piero ;
Saraswat, Krishna ;
Nishi, Yoshio .
JOURNAL OF APPLIED PHYSICS, 2009, 106 (10)
[8]  
Lee C.H., 2010, Proc. of IEEE IEDM Tech Digest, P416
[9]   New interface state density extraction method applicable to peaked and high-density distributions for Ge MOSFET development [J].
Martens, Koen ;
De Jaeger, Brice ;
Bonzom, Renaud ;
Van Steenbergen, Jan ;
Meuris, Marc ;
Groeseneken, Guido ;
Maes, Herman .
IEEE ELECTRON DEVICE LETTERS, 2006, 27 (05) :405-408
[10]  
Matsubara H., 2007, P SSDM, P18