Analysis and design of inductive coupling and transceiver circuit for inductive inter-chip wireless superconnect

被引：93

作者：

Miura, N ^{[1
]}

Mizoguchi, D

Sakurai, T

Kuroda, T

机构：

[1] Keio Univ, Dept Elect & Elect Engn, Yokohama, Kanagawa 2238522, Japan

[2] Univ Tokyo, Ctr Collaborat Res, Tokyo 1538505, Japan

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2005年 / 40卷 / 04期

关键词：

high bandwidth; inductor; low power; SiP; wireless bus;

D O I：

10.1109/JSSC.2005.845560

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A wireless bus for stacked chips was developed by utilizing inductive coupling among them. This paper discusses inductor layout optimization and transceiver circuit design. The inductive coupling is analyzed by a simple equivalent circuit model, parameters of which are extracted by a magnetic field model based on the Biot-Savart law. Given communication distance, transmit power, data rate, and SNR budget, inductor layout size is minimized. Two receiver circuits, signal sensitive and yet noise immune, are designed for inductive nonreturn-to-zero (NRZ) signaling where no signal is transmitted when data remains the same. A test chip was fabricated in 0.35-mu m CMOS technology. Accuracy of the models is verified. Bit-error rate is investigated for various inductor lavouts and communication distance. The maximum data rate is 1.25 Gb/s/channel. Power dissipation is 43 mW in the transmitter and 2.6 mW; in the receiver at 3.3 V. If chip thickness is reduced to 30 mu m in 90-nm device generation, power dissipation will be 1 mW/channel or bandwidth will be 1 Tb/s/mm(2).

引用

页码：829 / 837

页数：9

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