Power: A first-class architectural design constraint

被引:234
作者
Mudge, T [1 ]
机构
[1] Univ Michigan, Dept Comp Sci & Elect Engn, Ann Arbor, MI 48109 USA
关键词
D O I
10.1109/2.917539
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Limiting power consumption is a critical issue in computing, particularly in portable and mobile platforms such as laptop computers and cell phones. The internet use is growing exponentially, requiring server farms to match the accompanying demand for power. Organizing memory so that an access activates only parts of it can help to limit dynamic memory power loss. Several research efforts are underway to insert power estimators into cycle-level simulators for optimal power utilization.
引用
收藏
页码:52 / +
页数:8
相关论文
共 12 条
[1]   Address bus encoding techniques for system-level power optimization [J].
Benini, L ;
De Micheli, G ;
Macii, E ;
Sciuto, D ;
Silvano, C .
DESIGN, AUTOMATION AND TEST IN EUROPE, PROCEEDINGS, 1998, :861-866
[2]  
Brooks D, 2000, PROCEEDING OF THE 27TH INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE, P83, DOI [10.1145/342001.339657, 10.1109/ISCA.2000.854380]
[3]  
CAI G, 1999, COOL CHIPS TUTORIAL, P90
[4]   Energy dissipation in general purpose microprocessors [J].
Gonzalez, R ;
Horowitz, M .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1996, 31 (09) :1277-1284
[5]  
JOHNSON M, 2000, IEEE T COMPUT, P1
[6]  
LEFURGY C., 2000, P 6 INT S HIGH PERF, P218
[7]   Pipeline gating: Speculation control for energy reduction [J].
Manne, S ;
Klauser, A ;
Grunwald, D .
25TH ANNUAL INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE, PROCEEDINGS, 1998, :132-141
[8]   Self calibrating clocks for globally asynchronous locally synchronous systems [J].
Moore, SW ;
Taylor, GS ;
Cunningham, PA ;
Mullins, RD ;
Robinson, P .
2000 IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN: VLSI IN COMPUTERS & PROCESSORS, PROCEEDINGS, 2000, :73-78
[9]  
PARK A, 1992, P 25 INT S COMP ARCH, P1
[10]   Voltage scheduling in the IpARM microprocessor system [J].
Pering, T ;
Burd, T ;
Brodersen, R .
ISLPED '00: PROCEEDINGS OF THE 2000 INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN, 2000, :96-101