A 2.17-dB NF 5-GHz-band monolithic CMOS LNA with 10-mW DC power consumption

Design principles of CMOS low-noise amplifiers (LNAs) for simultaneous input impedance and noise matching by tailoring device size for R-opt = 50 Omega are introduced. It is found that R-opt close to 50 Omega can be obtained by using small devices (110 mum) and small currents (5 mA). Based on the proposed approach, CMOS LNAs with on-chip input and output matching networks on thin (similar to 20 mum) and normal (750 mum) substrates are implemented. It is found that the noise figure (NF) (3.0 dB) of the CMOS LNA at 5.2 GHz with 10-mW power consumption on the normal (750 mum) substrate can be reduced to 2.17dB after the substrate is thinned down to similar to 20 mum. The reduction of NF is attributed to the suppression of substrate loss of the on-chip inductors. The input return loss (S-11) is smaller than -22 dB across the entire band of interest (5,15-5.35 GHz). An input 1-dB compression point (P-1 (dB)) of -8.3 dBm and an input third-order intercept point of 0.8 dBm were also obtained for the LNA on the thin substrate.