Optimum device parameters and scalability of variable threshold voltage complementary MOS (VTCMOS)

被引：15

作者：

Hiramoto, T

Takamiya, M

Koura, H

Inukai, T

Gomyo, H

Kawaguchi, H

Sakurai, T

机构：

[1] Univ Tokyo, Inst Ind Sci, Meguro Ku, Tokyo 1538505, Japan

[2] Univ Tokyo, VLSI Design & Educ Ctr, Bunkyo Ku, Tokyo 1138656, Japan

[3] Univ Tokyo, Ctr Collaborat Res, Meguro Ku, Tokyo 1538505, Japan

来源：

JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS | 2001年 / 40卷 / 4B期

关键词：

variable threshold voltage complementary metal oxide semiconductor (VTCMOS); body effect factor; substrate bias; lowpower; high-speed; scalability; metal oxide semiconductor fieldeffect transistor (MOSFET);

D O I：

10.1143/JJAP.40.2854

中图分类号：

O59 [应用物理学];

学科分类号：

摘要：

The optimum device parameters of variable threshold voltage complementary metal oxide semiconductor (VTCMOS) have been investigated by means of device simulation and its scalability has been discussed. The optimum body effect factor depends on the relationship between the substrate bias and the supply voltage. It is shown that the VTCMOS scheme aiming at extremely low stand-by power will fail as the device size and the supply voltage are scaled. The advantage of VTCMOS will be its high speed, and the VTCMOS will be essential in high-speed circuits operating at a low supply voltage in combination with another low stand-by power scheme such as the insertion of leak cut-off switches.

引用

页码：2854 / 2858

页数：5

共 10 条

[1]

*AV CORP, 1998, MED VER 4 1

[2]

Hiramoto T, 2000, IEICE T ELECTRON, VE83C, P161

[3]

INUKAI T, 2000, CICC, P409

[4]

KAWAGUCHI H, 1998, IEEE INT SOL STAT CI, P192

[5] Optimum conditions of body effect factor and substrate bias in variable threshold voltage MOSFETs [J].

Koura, H ;

Takamiya, M ;

Hiramoto, T .

JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS, 2000, 39 (4B) :2312-2317

[6] A 0.9-V, 150-MHz, 10-mW, 4 mm(2), 2-D discrete cosine transform core processor with variable threshold-voltage (VT) scheme [J].

Kuroda, T ;

Fujita, T ;

Mita, S ;

Nagamatsu, T ;

Yoshioka, S ;

Suzuki, K ;

Sano, F ;

Norishima, M ;

Murota, M ;

Kako, M ;

Kinugawa, M ;

Kakumu, M ;

Sakurai, T .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1996, 31 (11) :1770-1779

[7]

MIYAZAKI M, 2000, ISSCC, P420

[8]

MIZUNO H, 1999, ISSCC, P280

[9]

OOWAKI Y, 1998, IEEE INT SOL STAT CI, P88

[10] CMOS with active well bias for low-power and RF/analog applications [J].

Wann, C ;

Harrington, J ;

Mih, R ;

Biesemans, S ;

Han, K ;

Dennard, R ;

Prigge, O ;

Lin, C ;

Mahnkopf, R ;

Chen, B .

2000 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, 2000, :158-159

← 1 →